1. Field of the Invention
The present invention relates to a memory array, particularly to a low-voltage EEPROM array.
2. Background of the Invention
The CMOS (Complementary Metal Oxide Semiconductor) process has been a common method for fabricating ASIC (Application Specific Integrated Circuit). The nonvolatile memories, such as the flash memory and EEPROM (Electrically Erasable Programmable Read Only Memory), are widely used in electronic products because the data thereinside can be electrically written and erased and because the data thereinside is saved when power is removed.
A nonvolatile memory is programmable, wherein electric charge is stored to vary the gate voltage of the transistors or not stored to keep the original gate voltage of the transistors. In an erase activity of a nonvolatile memory, the stored charge is eliminated to restore the original gate voltage of the transistors. The flash memory has advantages of smaller size and lower cost. However, the flash memory only supports large-area erasion. It is unlikely to erase the data of a specified memory cell of a flash memory, which causes some application inconveniences. EEPROM has a byte-write function and is more convenient than the flash memory. Refer to FIG. 1 and FIG. 2 for the circuit of a single-bit memory cell of EEPROM and the sectional view thereof. Each polysilicon memory cell of EEPROM comprises a memory transistor 10, a selection transistor 12 and a capacitor 13 arranged on the memory transistor 10. Owing to the abovementioned structure, EEPROM has a larger area than a flash memory. Further, the unselected sites need separating by transistors in a bit-erase activity of EEPROM, which increases the cost of EEPROM.
Accordingly, the present invention proposes a low-voltage EEPROM array to overcome the conventional problems.